Metal-oxide semiconductor (MOS) transistors include a gate electrode formed on a semiconductor substrate and a source/drain region formed in the semiconductor substrate adjacent to opposite sides of the gate electrode. The linewidth of the gate electrode may be an important dimension in the design of the device. As the size of MOS transistors has decreased, a corresponding reduction in the linewidth of the gate electrode has also occurred. As the linewidth of the gate electrode is reduced, the resistance of the gate electrode typically increases. This increased may resistance reduce the operation speed of the MOS transistor, making it difficult to achieve high speed devices.
A method of forming a gate electrode made of polycide has been proposed as a way to reduce the resistance of the gate electrode. The polycide layer has a structure in which a low-resistance metal silicide layer is stacked on a doped polysilicon layer. A MOS transistor having a conventional polycide gate electrode is illustrated in FIG. 1, and a cross-sectional view of the device taken along the line I-I′ of FIG. 1 is shown in FIG. 2.
As shown in FIGS. 1 and 2, a device isolation layer 2 is provided on predetermined regions of a semiconductor substrate 1 to define a plurality of active regions 3. A gate line 7 crosses over the active regions 3. The gate line 7 includes a gate insulating layer 4, a doped polysilicon layer 5, and a metal silicide layer 6 which are stacked on the semiconductor substrate 1 in the order named. The metal silicide layer 6 may be made of cobalt silicide. The doped polysilicon layer 5 and the metal silicide layer 6 together form the gate electrode of the MOS transistor. An impurity diffusion layer 8 is provided on the active regions 3 adjacent opposite sides of the gate line 7. The impurity diffusion layer 8 corresponds to the source/drain regions of the MOS transistor.
Since the metal silicide layer 6 has a lower resistance than the doped polysilicon layer 5, the metal silicide layer 6 acts to reduce the resistance of the gate electrode. As semiconductor devices have become more highly integrated, the linewidth of the gate line 7 has been reduced. As the linewidths are reduced, defects may appear in the metal silicide layer 6 that can result in a crack in the metal silicide layer 6 (the crack is denoted as “A” in FIGS. 1 and 2). The crack A can negatively impact operation of the device, particularly in the case where the linewidth of the gate line 7 is similar to the grain size of the metal silicide layer 6. Because of the crack A in the metal silicide layer 6, the resistance of the gate electrode may be significantly increased. As a result, the operation speed of the MOS transistor may be reduced.